Request for design guidance with FET source follower driver
#1 Request for design guidance with FET source follower driver
Inspired by Nick, I'm trying to get my head around the design of a FET source follower so I can give it a try. I kept coming back to Tubelab's Powerdrive SE page : http://tubelab.com/articles/circuits/power-drive/
I want to get the real basics right in my head first. The way George Broksie draws that circuit confuses me because I'm not familiar with the basics. Starter circuit attached.
300B operating point : 400Vak, -87Vgk, 60mA Ia, cathode grounded bar a 10R sense resistor.
Where Broksie draws "+ve Bias Supply" and "-ve Bias Supply" - that's one circuit right, providing and returning current through the FET ? That's why I've drawn it the way I have - to make that really clear (and allow someone to correct me if I misunderstood).
The max signal swing from the 45 (if the 26 and 45 are operating at full gain, which they won't be, but hey) is 174V pk. This is calculated as follows;
4.4Vrms balanced signal in from DAC. Input transformer SE output to 26 grid, 6.2Vpk. 26 amp factor 8 and 45 amp factor 3.5 : near as dammit exactly twice the proposed bias for the 300B. (Incidentally I'm currently biasing the 300B at -60V with 300Vak, I now realise I could be overloading it).
Anyway back to the FET. So the FET source needs to swing from 0v to -174v. Hence for now I've shown the FET supply as 0/-200v.
In DIYAUDIO forum, April this year, Broksie recommended this FET as his current choice : https://www.mouser.co.uk/ProductDetail/511-STF3LN80K5
How to choose the FET source load ? Starting with 10k, purely from an old Powerdrive diagram.
So with no signal, I want the FET source to be at -87v, so a 113v drop across the FET Source Load. Using 10k that means I want 11.3mA flowing through the FET. At the extremes of signal swing following the same approach I want the current through the FET to vary between 2.6mA and 20mA controlled by the voltage on the FET gate.
What voltage will there be across the FET drain-source ? The datasheet has a chart for "Output characteristics" which shows Id against Vds for different Vgs - but I don't think that helps me ? The Rds (on) is 2.667 - does that show me the Vds for a specific Id ? The curves for low current look like a straight line which follows this so I think that's it. With 20mA flowing there should be 53mVds - tiny so I'll ignore.
So how do I work out what voltages are needed on the gate ? I can't see anything on the datasheet which will help me figure out what voltage I need on the gate to cause the current flows I need.
Once I know the range of gate voltages I need I can figure out what bias range adjustment is needed - right ? Hang on - the 174V max swing from the 45 anode is going to appear on the FET gate, albeit swinging about a figure set by the FET bias divider.
I think I may have gone off track - someone get me back on the rails please ?
I want to get the real basics right in my head first. The way George Broksie draws that circuit confuses me because I'm not familiar with the basics. Starter circuit attached.
300B operating point : 400Vak, -87Vgk, 60mA Ia, cathode grounded bar a 10R sense resistor.
Where Broksie draws "+ve Bias Supply" and "-ve Bias Supply" - that's one circuit right, providing and returning current through the FET ? That's why I've drawn it the way I have - to make that really clear (and allow someone to correct me if I misunderstood).
The max signal swing from the 45 (if the 26 and 45 are operating at full gain, which they won't be, but hey) is 174V pk. This is calculated as follows;
4.4Vrms balanced signal in from DAC. Input transformer SE output to 26 grid, 6.2Vpk. 26 amp factor 8 and 45 amp factor 3.5 : near as dammit exactly twice the proposed bias for the 300B. (Incidentally I'm currently biasing the 300B at -60V with 300Vak, I now realise I could be overloading it).
Anyway back to the FET. So the FET source needs to swing from 0v to -174v. Hence for now I've shown the FET supply as 0/-200v.
In DIYAUDIO forum, April this year, Broksie recommended this FET as his current choice : https://www.mouser.co.uk/ProductDetail/511-STF3LN80K5
How to choose the FET source load ? Starting with 10k, purely from an old Powerdrive diagram.
So with no signal, I want the FET source to be at -87v, so a 113v drop across the FET Source Load. Using 10k that means I want 11.3mA flowing through the FET. At the extremes of signal swing following the same approach I want the current through the FET to vary between 2.6mA and 20mA controlled by the voltage on the FET gate.
What voltage will there be across the FET drain-source ? The datasheet has a chart for "Output characteristics" which shows Id against Vds for different Vgs - but I don't think that helps me ? The Rds (on) is 2.667 - does that show me the Vds for a specific Id ? The curves for low current look like a straight line which follows this so I think that's it. With 20mA flowing there should be 53mVds - tiny so I'll ignore.
So how do I work out what voltages are needed on the gate ? I can't see anything on the datasheet which will help me figure out what voltage I need on the gate to cause the current flows I need.
Once I know the range of gate voltages I need I can figure out what bias range adjustment is needed - right ? Hang on - the 174V max swing from the 45 anode is going to appear on the FET gate, albeit swinging about a figure set by the FET bias divider.
I think I may have gone off track - someone get me back on the rails please ?
Last edited by RhythMick on Fri Jun 05, 2020 8:14 pm, edited 3 times in total.
- pre65
- Amstrad Tower of Power
- Posts: 21400
- Joined: Wed Aug 22, 2007 11:13 pm
- Location: North Essex/Suffolk border.
#2 Re: Request for design guidance with FET source follower driver
The only thing necessary for the triumph of evil is for good men to do nothing.
Edmund Burke
G-Popz THE easy listening connoisseur. (Philip)
Edmund Burke
G-Popz THE easy listening connoisseur. (Philip)
#3 Re: Request for design guidance with FET source follower driver
Ha - thanks, you posted that as I was typing my brain-dump of where I think I'm up to.pre65 wrote: ↑Fri Jun 05, 2020 7:44 pm The type I first found was named "power-drive".
http://tubelab.com/articles/circuits/power-drive/
- izzy wizzy
- Old Hand
- Posts: 1496
- Joined: Fri Nov 02, 2007 7:02 pm
- Location: Auckland NZ
- Contact:
#4 Re: Request for design guidance with FET source follower driver
And http://www.bartola.co.uk/valves/for-sal ... lower-pcb/
Down a bit are links to further reading/homework
Down a bit are links to further reading/homework
#5 Re: Request for design guidance with FET source follower driver
You need the drain of the fet to be > 0v or you won;t be able to swing to source up to 0v.
Whenever an honest man discovers that he's mistaken, he will either cease to be mistaken or he will cease to be honest.
#7 Re: Request for design guidance with FET source follower driver
Looking forward to it - many thanksizzy wizzy wrote: ↑Fri Jun 05, 2020 8:10 pm And http://www.bartola.co.uk/valves/for-sal ... lower-pcb/
Down a bit are links to further reading/homework
#8 Re: Request for design guidance with FET source follower driver
See again, something I'm struggling with here. If the source is at 0v and the supply is +200V, so Vds is 200V ? Vds will swing to 374v - Is that right ? I can see from the datasheet that it will withstand that (800V max) but it doesn't compute with me. My basic understanding isn't right. Off to do more reading on MOSFETs.
#9 Re: Request for design guidance with FET source follower driver
To repeat something that others have heard before. There is no zero. Its just a convenience we chose to call a point in the circuit zero. Voltage is always the difference between two points. If it helps, think of the -200v line as zero, then what was zero becomes +200v, and the line the FET drain is connected to is +400v
Just what bit of that doesn’t compute? If the gate is taken to -174 (ish) volts, the the source will be at or about -174, the source is following the gate. If the source is at -175v and the drain at +200, the Vds (the voltage between drain and source) is 200 - -174, or 200 + 174 = 374.See again, something I'm struggling with here. If the source is at 0v and the supply is +200V, so Vds is 200V ? Vds will swing to 374v - Is that right ? I can see from the datasheet that it will withstand that (800V max) but it doesn't compute with me
Without being factious. Maybe you need to understand voltage first. Once you have that it all becomes simple.Off to do more reading on MOSFET
Whenever an honest man discovers that he's mistaken, he will either cease to be mistaken or he will cease to be honest.
#10 Re: Request for design guidance with FET source follower driver
Sorry Nick no that's not it. It's not the "where you reference zero" either.
Something in my head just hasn't properly got the behaviour of solid state components. For a valve cathode follower I can draw a load line and see how current relates to grid voltage. For some reason I can't picture how a voltage potential difference exists between drain and source, which are separated only by a gate. Maybe I shouldn't try to picture it.
Something in my head just hasn't properly got the behaviour of solid state components. For a valve cathode follower I can draw a load line and see how current relates to grid voltage. For some reason I can't picture how a voltage potential difference exists between drain and source, which are separated only by a gate. Maybe I shouldn't try to picture it.
#11 Re: Request for design guidance with FET source follower driver
OK so let's go to an easier question (perhaps).
How do you choose the Source Load resistor for a particular FET and circuit requirement ?
How do you choose the Source Load resistor for a particular FET and circuit requirement ?
#12 Re: Request for design guidance with FET source follower driver
Actually Nick you did it with the phrase "source follows gate". Obvious, but for some reason I was looking for curves to show me an amplification effect. Nonsense, I was just not looking at it right.
Sorry
Sorry
#13 Re: Request for design guidance with FET source follower driver
Trying to think why you thought I didn't understand voltage.
Please reassure me I'm right that the current through the source load will change as the signal varies the voltage on the 300B grid ?
Bottom end of that resistor is connected to -200v. Top end will be between -174v and 0v, so between 26v and 200v across that load resistor. Therefore the current will vary - right ?
#14 Re: Request for design guidance with FET source follower driver
Because of this:Trying to think why you thought I didn't understand voltage.
When in reality I didn't understand what you were saying. Still don't from the above TBH.If the source is at 0v and the supply is +200V, so Vds is 200V ? Vds will swing to 374v - Is that right
Yes. And with that range, I still think a current source would be a better choice.Bottom end of that resistor is connected to -200v. Top end will be between -174v and 0v, so between 26v and 200v across that load resistor. Therefore the current will vary - right
Whenever an honest man discovers that he's mistaken, he will either cease to be mistaken or he will cease to be honest.
#15 Re: Request for design guidance with FET source follower driver
Ok thanks Nick. As usual I'm not explaining myself. I need to go experiment, Spice first.