even more lateral fets

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ed
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#46 Re: even more lateral fets

Post by ed »

grrrr grrrr grrr.....it's almost like you guys are in my head..

for the last 2 days I've been doing the mental gymnastics with exactly the thoughts just mentioned...

I've simmed every buffer method I can think of but they all add complication and extra circuit in the path.
I started with the simple jfet buffer idea just to isolate the output of the opamp from the input of the fet with no capacitive load on the opamp.
I then finally arrived at putting a B1 circuit between the opamp and the fet...

but it all adds complexity.

back to simple is best, look at the requirements, what is needed is:

a simple circuit with a gain of 3 with high input impedance and low enough output impedence to drive a fet.
It must swing line level input i.e 2v rms.
have distortion and speed figure as good as possible because that's what I wanted from the opamp...

not too much to ask for......but but

I would go with a simple bjt vas ..but for some reason I have a prejudice against bjts and I'll avoid if possible. I think I picked up this prejudice from Douglas Self as he mentions his prejudice against fets and it was like a red rag to a bull. Only difference is that he understands what he's doing. Like the obstnate child that I am..he says yes so I immediately say no.

at the moment I'm still pursuing the simplest buffer....Despite my prejudice I still may end up with an emitter follower like Mike suggested.
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#47 Re: even more lateral fets

Post by ed »

continuing to play with emitter follower...
bjts, nasty little things, just like hobbitses
the output cap does modify it slightly but the behaviour remains
has anybody seen this behaviour before, or suggest possible reasons for it?

10k sq.jpg
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#48 Re: even more lateral fets

Post by ed »

I think I may have found the answer to the question above.
It may be down to stray capacitance in the bjt load resistor.
in my case I currently have 3 resistors in parallel to minimise heat and avoid another heat sink.
I don't fully understand the principal but I'm creeping up on it.

mm..replace the emitter load with a current mirror...I wonder...

whoever said a little knowledge is a dangerous thing was right on the money

don't give up hope there is more to come
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#49 Re: even more lateral fets

Post by ed »

ah ha...there's more
with the coupling cap I get this...
xxxxxx.jpg
xxxxxx.jpg (181.65 KiB) Viewed 5818 times
and without the coupling cap the output follows the input correctly.
I'm at the limit of my understanding now.....can anybody elaborate on this behaviour?
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#50 Re: even more lateral fets

Post by Nick »

can anybody elaborate on this behaviour
Caps don't pass DC, so I don't see why you would expect anything different. The output is ramping towards a net DC value of 0v.
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#51 Re: even more lateral fets

Post by ed »

Nick wrote: Tue May 02, 2023 12:05 pm
can anybody elaborate on this behaviour
Caps don't pass DC, so I don't see why you would expect anything different. The output is ramping towards a net DC value of 0v.
many thanks...

I wasn't aware that a square wave was considered to have a dc component...but having read some more I see lots of people consider it the mean or average.

I originally wanted to pursue something that defied the formula that anything of quality had to be complex. It seems that my original quest was thwarted by the need for ever more complex adjustments. Yes I could pursue a different front end but it would be a more complex solution and I already have 9 amplifiers sitting here that achieve that. In addition, if I learn anything in the process I will be satisfied for a short while but I will have forgotten it in a fortnight.....

I will now reconsider the mofo project...
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#52 Re: even more lateral fets

Post by Nick »

I wasn't aware that a square wave was considered to have a dc component
Well, it does as you have it as its going from 0v to 1v (or some +ve value), it it goes from -1v to +1v then there is no net DC component.
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#53 Re: even more lateral fets

Post by Nick »

I see lots of people consider it the mean or average
Well, I would hope ALL people would consider it having a DC offset if they were in any sense rational.
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#54 Re: even more lateral fets

Post by ed »

My bad!!

please read my sentence to be 'some people refer to it' rather than 'some people consider it'

further with the dc and square wave , I realise now that I wasn't feeding it a balanced square wave. I have now woken up a bit and realise that even if I get spice to supply a balanced square wave the gain from the buffer will never be 1 due to the DC shift caused by the transistors Vbe threshold, so the square wave will always be offset by 0.6v or so.

and now I'm really out of my depth...

at 10k square wave spice likes my buffer after 50ms, at which point it settles and the output follows the input with a coupling cap. Do you think this Is valid, and would it pass the square wave test in a real situation.
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#55 Re: even more lateral fets

Post by Nick »

Not sure TBH what you are asking, I would expect reality to do what you are seeing, its just the time constant of the RC doing what you would expect.
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#56 Re: even more lateral fets

Post by Mike H »

SteveH wrote: Sun Apr 30, 2023 8:39 pm MOsfet FOllower?
Thanks, until the next time! Memory of a goldfish. :lol:

Actually goldfish are quite good at remembering things, as was proved by the Myth Busters guys... :D
 
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#57 Re: even more lateral fets

Post by Mike H »

Nick wrote: Sun Apr 30, 2023 9:37 pm
IMO the original is 'nearly there' - I would now look at an emitter follower between the op-amp and the FET, could have just an emitter resistor for simplicity, but would decouple the gate capacitance from the op-amp?
This is the sort of mental gymnastics I go through now and then and eventually get back to: "or I could just use the push pull amp I have".

Does make the valve front end that Steve is using, look like a simple solution to the problem. Maybe a Pass labs B1 would do the job between the op amp and the mosfet. Actually, the B1 would work well, could directly couple to the mosfet and the current source load in the B1 would mean that the mosfet bias could be added before the jfet buffer.
That's a thought, just do away with the op-amp?
 
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#58 Re: even more lateral fets

Post by Mike H »

ed wrote: Tue May 02, 2023 11:39 am ah ha...there's more
with the coupling cap I get this...

xxxxxx.jpg

and without the coupling cap the output follows the input correctly.
I'm at the limit of my understanding now.....can anybody elaborate on this behaviour?
You have to allow for the DC operating conditions to settle after start up. I've had this kind of thing frequently too. What I tend to do now is, delay the input signal for a second or so, thus allowing time for the circuit to bias itself to stable DC.

BTW I notice with Q2 and Q3 you have created a current mirror, viz, the Ice of both is the same because the Vbe of both is the same, but this only works with bjt's on the same silicon chip, because they have idential characteritics, this will not work with discrete components.
 
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#59 Re: even more lateral fets

Post by Mike H »

I would do this...

-
Current source.jpg
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-
Ice of Q1 is determined by Vbe of Q1 / value of R2.
 
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#60 Re: even more lateral fets

Post by Nick »

Well to be picky it's the Vbe of Q2/R2.

And I disagree, current mirrors are just fine with discrete devices. Having them thermally coupled is a good thing and having the two devices on one die will do that just fine. But the Vbe is set by the band gap of the PN junction so it just about always 0.6v for silicon. Having the forward current gain matched is also important and that's one area temp matters.

More complex mirrors exist of course
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